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Workshop Organizers:
Rainer Buchty
Karlsruhe Institute of Technology, Germany
Jan-Philipp Weiß
Karlsruhe Institute of Technology, Germany
Steering Committee:
Jürgen Becker
Karlsruhe Institute of Technology, Germany
Vincent Heuveline
Karlsruhe Institute of Technology, Germany
Wolfgang Karl
Karlsruhe Institute of Technology, Germany
Jan-Philipp Weiß
Karlsruhe Institute of Technology, Germany
Program Committee:
Mladen Berekovic
Univ. Braunschweig, Germany
Alan Berenbaum
SMSC, USA
Nevin Heintze
Google Inc.
Vincent Heuveline
Karlsruhe Institute of Technology, Germany
Eric D'Hollander
Ghent University, Belgium
Ben Juurlink
TU Delft, The Netherlands
Paul Kelly
Imperial College, UK
Wolfgang Karl
Karlsruhe Institute of Technology, Germany
Richard Kaufmann
Hewlett-Packard, USA
Hsin-Ying Lin
Intel, USA
Rudolf Lohner
Karlsruhe Institute of Technology, Germany
Andy Nisbet
Manchester Metropolitan University, UK
Ulrich Rüde
Universität Erlangen-Nürnberg, Germany
Martin Schulz
LLNL, USA
Thomas Steinke
Zuse-Institut Berlin, Germany
Robert Strzodka
Max Planck Institut Informatik, Germany
Stephan Wong
TU Delft, The Netherlands
Important Dates:
Paper Submission Deadline:
September 1, 2008
Notification of Acceptance:
September 29, 2008
Camera-ready papers:
October 8, 2008
Contact:
Rainer Buchty
Karlsruhe Institute of Technology, Germany
rainer.buchty@kit.edu
Jan-Philipp Weiß
Karlsruhe Institute of Technology, Germany
jan-philipp.weiss@kit.edu
Submission Address:
submission@hiphac.org
Workshop Program (PDF):
http://www.hiphac.org/program/
Workshop Website:
http://www.hiphac.org/
Conference Website:
http://www.microarch.org/micro41/
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Workshop theme: Heterogeneity and reconfigurability in computer
systems are growing. Multi- and manycore-based systems are complemented by
coprocessors, accelerators, and reconfigurable units providing huge
computational power. However, applications of scientific interest (e.g. in
high-performance computing and numerical simulation) are not yet ready to
exploit the available high computing potential. Different programming
models, non-adjusted interfaces, and bandwidth bottlenecks complicate
holistic programming approaches for heterogeneous architectures. In modern
microprocessors, hierarchical memory layouts and complex logics obscure
predictability of memory transfers or performance estimations.
This workshop aims at combining new aspects of parallel, heterogeneous, and
reconfigurable microprocessor technologies with concepts of high-performance
computing and, particularly, numerical solution methods. Compute- and
memory-intensive applications can only benefit from the full hardware
potential if all features on all levels are taken into account in a holistic
approach.
Workshop Program
Opening Session
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13:30 |
Welcome, Introduction & Overview |
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13:40 |
Keynote Talk: Multicore and accelerators for scientific
computing -- romance or marriage of convenience?
Vincent Heuveline, Karlsruhe Institute of Technology |
Session I: Architecture
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14:40 |
OROCHI: A Multiple Instruction Set SMT Processor
T. Nakada, Y. Nakashima, H. Shimada, K. Kise, T. Kitamura; Nara Institute of Science and Technology |
Coffee Break (15:00-15:30)
Session II: Stream Processing and Numerical Computation
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15:30 |
Experiences with Numerical Codes on the Cell Broadband Engine Architecture
M. Stürmer, D. Ritter, H. Köstler, U. Rüde; Univ. Erlangen-Nürnberg |
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15:50 |
A Realtime Ray Casting System for Voxel Streams on the Cell Broadband Engine
V. Fuetterling, C. Lojewski; Fraunhofer ITWM |
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16:10 |
Comparison of High-Speed Ray Casting on GPU using CUDA and OpenGL
A. Weinlich, B. Keck, J. Hornegger; Univ. Erlangen-Nürnberg |
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16:30 |
RapidMind Stream Processing on the PlayStation 3 for a 3D Chorin-based Navier-Stokes Solver
V. Heuveline, D. Lukarski, J.-P. Weiß; Karlsruhe Institute of Technology |
Short Break (16:50-17:00)
Session III: Temporal Locality
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17:00 |
Optimising Component Composition using Indexed Dependence Metadata
L.W. Howes, A. Lokhmotov, P.H.J. Kelly, A.J. Field; Imperial College London |
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17:20 |
Accelerating Stencil-Based Computation by Increased Temporal Locality on Modern Multi- and Many-Core
Architectures
M. Christen, O. Schenk, P. Messmer, E. Neufeld, H. Burkhart; Univ. Basel |
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17:40 |
Fast Cache-Miss Estimation of Loop Nests using Independent Cluster
Sampling
K. Sharma, S. Aggarwal, M. Chaudhuri, S. Ganguly;
Indian Institute of Technology Kanpur |
Closing Session
The selected papers are published as printed workshop proceedings
(ISBN 978-3-86644-298-6) through Karlsruhe
University Press.
You can order your individual copy from here
or download the proceedings for free
In case of any questions please contact the
workshop organizers.
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